The present invention relates to a semiconductor device; and, more particularly, to a Complementary Metal Oxide Semiconductor (CMOS) image sensor.
Recently, with development of multimedia communication via internet, the demand on digital cameras is dramatically increased. Furthermore, as the supply of the mobile communications terminals such as a Personal Digital Assistant (PDA), an International Mobile Telecommunications-2000 (IMT-2000) cellular phones, and a Code Division Multiple Access (CDMA) terminal is increased, the demand of the small-sized camera modules is increased. Most camera modules basically include an image sensor. Generally, the image sensor is a device to convert optical image into an electrical signal, and a charge coupled device (hereinafter, referred to as “CCD”) and a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor are widely used as the image sensor.
The driving method of the CCD is complicated and high power consumption is required. Further, the CCD is required to take lots of mask processes and has the disadvantages in that it is difficult to implement one-chip integration of the signal processing circuits. Recently, the CMOS image sensor has been occupied the attention of the image sensor techniques because it is relatively easy to implement the monolithic integration of the signal processing circuits including a controller and a driver. Moreover, the CMOS image sensor can be manufactured with the cost-effective circuit implementation in the low-power operation, low power consumption, the compatibility with other peripheral circuits and standardized fabrication processes.
However, in the CMOS image sensor, the analog signal generated by a light receiving element, for example, a photo diode is generated with various parasitic effects caused by a parasitic capacitance, a resistance, an inconsistency of a semiconductor device characteristic, a dark current leakage and so on. Since the parasitic effects are inevitably generated in the semiconductor device, they bring about degradation of the signal-to-noise of the image data. Therefore, the noise is a critical factor to limit the performance of the CMOS image sensor.
The noises caused in the CMOS image sensor can be classified into the kT/C noise related to the image data sampling, the 1/f noise related to a circuit which is used for amplifying the image signal and the fixed pattern noise (hereinafter, referred to as FPN) related to an inconsistency of the signal processing circuits of a sensor. The FPN of them is not very good to a visual since it appears in the picture on which peoples can directly recognize the noise as a strip or perpendicular line.
FIG. 1 is a block diagram illustrating a conventional CMOS image sensor having a rectangular unit pixel structure. Referring to FIG. 1, in the case where a row address signal is applied to a decoder with a pixel array 10 as the central figure, a row decoder 20 is disposed in one direction of the pixel array 10, a pixel data output is disposed at right angles with the row decoder 20, and a column decoder 30 producing a column address signal of the pixel is also disposed centering around the pixel array 10.
The data read-out procedure of the CMOS image sensor in FIG. 1 will be described. First, data is read out from one pixel by selecting both a first row which is selected by the row decoder 20 and a first column which is selected by the column decoder 30 and, thereafter, the read-out data is amplified. Next, a second row is selected by the row decoder 20, a second column is selected by the column decoder 30, and data of another pixel is read out and amplified. In such a manner that the pixel is selected by the row and column decoders 20 and 30, the whole pixels are read out and amplified one by one. The CMOS image sensor has the various kinds of unit pixels. The general unit pixels are formed in two types of 3-T (transistors) and 4-T structures. The 3-T structure has one photodiode and three transistors and the 4-T structure has one photodiode and four transistors.
FIG. 2 is a circuit diagram illustrating the 3-T structure of the CMOS image sensor. Referring to FIG. 2, the pixel in the 3-T structure has one photodiode to convert photogenerated charges into an electric signal and three NMOS transistors to process this electric signal. The three transistors are called a reset transistor Rx, a drive transistor Dx and a select transistor Sx, respectively. The reset transistor Rx resets the photodiode connected to a ground voltage by applying a power supply voltage VDD to one end of the photodiode. The drive transistor Dx forms a source follower which acts as a buffer amplifier and the select transistor Sx acts as a switch for addressing the pixel.
FIG. 4 is a circuit diagram illustrating the 4-T structure of the CMOS image sensor. Referring to FIG. 4, the pixel in the 4-T structure has one photodiode to convert photogenerated charges into an electric signal and four NMOS transistors to process this electric signal. The four transistors are called a transfer transistor Tx, a reset transistor Rx, a drive transistor Dx and a select transistor Sx, respectively. The transfer transistor Tx transfers photogenerated charges in the photodiode to a floating diffusion region FD and the reset transistor Rx sets a potential of the floating diffusion region FD to a predetermined value and then resets the floating diffusion region FD. The drive transistor Dx, as a source follower, acts as a buffer amplifier based on the accumulated charges on the floating diffusion region FD. In similar to the 3-T structure, the select transistor Sx in the 4-T structure acts as a switch for addressing the pixel.
The most important difference between the 3-T and 4-T structures is the presence of the transfer transistor Tx and the floating diffusion region FD. The 3-T structure turns on the reset transistor Rx after detecting a reset level of the unit pixel; however, the 4-T structure detects the signal level by turning on the transfer transistor Tx after detecting the reset level by turning on the reset transistor Rx.
FIG. 3 is a circuit diagram illustrating a pixel array in which one column line is commonly owned by a plurality of pixels in the 3-T structure. As shown in FIG. 3, the unit pixels UP1 to UPn are commonly connected to one column line and then connected to one load transistor.
FIG. 5 is a circuit diagram illustrating the pixel array in which the pixels of the 4-T structure are commonly connected to one column line. Referring to FIG. 5, the unit pixels UP1 to UPn are commonly connected to one column line and connected to one load transistor.
As shown in FIGS. 3 and 5, in the 3-T and 4-T structures, a plurality of pixels are commonly connected to one column line and connected to one load transistor through the column line. The data are outputted on a column-by-column basis as shown in FIG. 1.
The CMOS image sensor having these characteristics and configuration has the disadvantage in that the dynamic range of the CMOS image sensor is lower than that of the CCD (approximately, a half (½)). The dynamic range means the rate of the saturation level of the pixel to the signal noise level and it is the significance factor to determine the chroma of the color.
If approximately 20 million electrons are detected at the saturation and approximately 40 electrons are detected at the noise, the dynamic range is about 5000 and the noise is −75 dB. Since the variation of the transistors which is employed for converting the photogenerated charges into a voltage level has an effect on the output characteristics of CMOS image sensor, the CMOS image sensor has the disadvantage in the dynamic range, as compared with the CCD.